Wiring board

ABSTRACT

A wiring board includes a core substrate having a number of through-holes, and buildup insulating layers and buildup wiring layers alternately laminated on upper and lower surfaces of the core substrate, in which a first through-hole group is arranged in a first region in the core board at a first arrangement density, the first region being opposed to the semiconductor element connection pad formation region, a second through-hole group is arranged in a second region at a second arrangement density lower than the first arrangement density, the second region being located in an outer peripheral portion of the core substrate and away from the first region, and a third through-hole group is arranged in a third region at a third arrangement density higher than the second arrangement density, the third region being located between the first region and the second region.

FIELD OF INVENTION

The present invention relates to a wiring board for mounting asemiconductor element such as a semiconductor integrated circuitelement.

BACKGROUND

As described in JP 2001-7155 A, a flip-chip bonding is conventionallyknown as a mounting method for mounting a semiconductor element such asa semiconductor integrated circuit element on a wiring board.

As the wiring board used in the flip-chip bonding, a wiring board formedby a buildup method is known. FIG. 4 is a schematic cross-sectional viewshowing a conventional wiring board 20 formed by the buildup method.FIG. 5 is a horizontal cross-sectional view of the wiring board 20 takenalong line I-I in FIG. 4.

As shown in FIG. 4, the conventional wiring board 20 includes buildupinsulating layers 12 and buildup wiring layers 13 alternately laminatedon upper and lower surfaces of a core substrate 11.

A core conductor layer 14 made of copper foil or a copper plating layeris adhered to the upper and lower surfaces of the core substrate 11. Inaddition, a number of through-holes 15 are formed so as to extend fromthe upper surface to the lower surface of the core substrate 11, and thecopper plating layer serving as a part of the core conductor layer 14 isadhered to an inside of the through-hole 15. The through-hole 15 isfilled with a resin.

A plurality of via-holes 16 are formed in each buildup insulating layer12. The buildup wiring layer 13 made of a copper plating layer is formedon and adhered to a surface of the buildup insulating layer 12 includingthe via-holes 16.

The vertically adjacent buildup wiring layers 13, 13 are electricallyconnected to each other through the via-holes 16. The buildup wiringlayer 13 is electrically connected to the through-holes 15. A part ofthe outermost buildup wiring layer 13 located on a side of an uppersurface of the wiring board 20 is formed as circular semiconductorelement connection pads 17 which are electrically connected toelectrodes T of a semiconductor element S. These semiconductor elementconnection pads 17 are arranged in a lattice-like form so as tocorrespond to the electrodes T of the semiconductor element S, in asemiconductor element connection pad formation region A which is asquare region corresponding to the semiconductor element S. A part ofthe outermost buildup wiring layer 13 located on a side of a lowersurface of the wiring board 20 is formed as circular external connectionpads 18 which are each electrically connected to a wiring conductor ofan external electric circuit board (not shown). These externalconnection pads 18 are arranged in a lattice-like form.

Solder resist layers 19 are adhered to the outermost buildup insulatinglayer 12 and the buildup wiring layer 13 formed thereon except for theexposed semiconductor element connection pad 17 and external connectionpad 18. A soldering bump B is welded to the semiconductor elementconnection pad 17 which is not covered with the solder resist layer 19.The electrode T of the semiconductor element S is electrically connectedto the exposed semiconductor element connection pad 17 through thesoldering bump B. The exposed external connection pad 18 which is notcovered with the solder resist layer 19 is connected to the wiringconductor of the external electric circuit board (not shown) through asoldering ball.

In the meantime, in order to ensure sufficient power supply from thewiring board 20, many semiconductor elements S have a terminalarrangement in which a number of grounding and power supply electrodes Tare provided in a center of its lower surface, and a number of signalelectrodes T are provided in an outer peripheral portion of its lowersurface.

When such a semiconductor element S is mounted on the wiring board, asshown in FIG. 5, grounding through-holes 15G and power supplythrough-holes 15P are provided in a region X opposed to thesemiconductor element connection pad formation region A, at a higharrangement density. Meanwhile, signal through-holes 15S are provided inan outer peripheral portion of the core substrate 11 outside the regionX, at a low arrangement density. Since the grounding through-holes 15Gand the power supply through-holes 15P are provided in the region Xopposed to the semiconductor element connection pad formation region A,at the high arrangement density, it is possible to connect the groundingsemiconductor element connection pad 17 to the grounding through-hole15G, and the power supply semiconductor element connection pad 17 to thepower supply through-hole 15P within a short distance.

Furthermore, the grounding external connection pads 18 and the powersupply external connection pads 18 are arranged in a center of the lowersurface of the wiring board 20. Thus, it is possible to connect thegrounding through-hole 15G to the grounding external connection pad 18,and the power supply through-hole 15P to the power supply externalconnection pad 18 within a short distance. As a result, an inductance islow in each of current paths for connecting the grounding semiconductorelement connection pad 17 to the grounding external connection pad 18,and the power supply semiconductor element connection pad 17 to thepower supply external connection pad 18, so that the power can besufficiently supplied to the semiconductor element S.

As shown in JP 2011-159734 A, according to the conventional wiringboard, the arrangement density of the through-holes 15 is higher in theregion X of the core substrate which is opposed to the semiconductorelement connection pad formation region A, and is lower in the regionoutside the region X. However, behaviors of thermal expansion andthermal shrinkage, and stiffness differ between the region having thehigh arrangement density of the through-holes 15 and the region havingthe low arrangement density thereof. The difference in behaviors of thethermal expansion and thermal shrinkage, and the difference in stiffnessbecome a factor that causes warpage in the wiring board 20 when theelectrode T of the semiconductor element S is connected to thesemiconductor element connection pad 17 through the soldering bump B.

Therefore, when the semiconductor element S is mounted on theconventional wiring board 20, the upper surface of the wiring board 20is warped and recessed warpage is generated as shown in FIG. 6. Whensuch recessed warpage is generated, a distance is reduced between theelectrode T of the semiconductor element S and the semiconductor elementconnection pad 17 formed in an outer peripheral portion in thesemiconductor element connection pad formation region A, so that thesoldering bump B is severely crushed. When the soldering bumps Badjacent to each other are severely crushed, these soldering bumps Bcome in contact with each other to cause an electrical short circuit. Asa result, the semiconductor element S cannot be normally operated.

SUMMARY

An object of the present invention is to provide a wiring board in whicha soldering bump is not severely crushed when an electrode of asemiconductor element is connected to a semiconductor element connectionpad through the soldering bump, so that an electrical short circuit isnot caused between the soldering bumps, and the mounted semiconductorelement can be normally operated.

A wiring board of the present invention includes a core substrate havinga number of through-holes, and buildup insulating layers and buildupwiring layers alternately laminated on upper and lower surfaces of thecore substrate. The wiring board has a semiconductor element connectionpad formation region including a number of semiconductor elementconnection pads made of the buildup wiring layer and arranged in acenter of an upper surface in a lattice-like form, in which a firstthrough-hole group is arranged in a first region in the core substrateat a first arrangement density, the first region being opposed to thesemiconductor element connection pad formation region, a secondthrough-hole group is arranged in a second region at a secondarrangement density lower than the first arrangement density, the secondregion being located in an outer peripheral portion of the coresubstrate and away from the first region, and a third through-hole groupis arranged in a third region at a third arrangement density higher thanthe second arrangement density, the third region being located betweenthe first region and the second region.

According to the wiring board of the present invention, the thirdthrough-hole group is arranged in the third region located between thefirst region and the second region, at the third arrangement densityhigher than the second arrangement density. Thus, behaviors of thermalexpansion and thermal shrinkage and a position of a stiffness change dueto the difference in arrangement density of the through-holes areprovided in a region away from the semiconductor element connection padformation region. As a result, when the electrode of the semiconductorelement is connected to the semiconductor element connection pad throughthe soldering bump, an impact on the semiconductor element connectionpad formation region becomes small, and warpage can be made small in thesemiconductor element connection pad formation region. As a result, itis possible to prevent the distance from being reduced between theelectrode of the semiconductor element and the semiconductor elementconnection pad provided in an outer peripheral portion, so that thesoldering bump is not severely crushed. Therefore, an electrical shortcircuit is not caused between the adjacent soldering bumps, and themounted semiconductor element can be normally operated.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic cross-sectional view showing one embodiment of awiring board according to the present invention;

FIG. 2 is a horizontal cross-sectional view taken along line I-I in FIG.1;

FIG. 3 is a schematic cross-sectional view showing a state in which asemiconductor element is mounted on the wiring board according to theone embodiment of the present invention;

FIG. 4 is a schematic cross-sectional view showing a conventional wiringboard;

FIG. 5 is a horizontal cross-sectional view taken along line I-I in FIG.4; and

FIG. 6 is a schematic cross-sectional view showing a state in which asemiconductor element is mounted on the conventional wiring board.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, a wiring board according to the present invention will bedescribed in detail with reference to the drawings. FIG. 1 is aschematic cross-sectional view showing a wiring board 10 according toone embodiment of the present invention. FIG. 2 is a horizontalcross-sectional view taken along line I-I in FIG. 1.

As shown in FIG. 1, the wiring board 10 includes a core substrate 1, anda plurality of buildup insulating layers 2 and a plurality of buildupwiring layers 3 which are alternately laminated on upper and lowersurfaces of the core substrate 1.

The core substrate 1 has a thickness of about 50 μm to 800 μm. The coresubstrate 1 is an insulating board made of an electric insulatingmaterial obtained by impregnating glass cloth having glass fiber bundleswoven vertically and horizontally, with a thermosetting resin such as abismaleimide triazine resin or an epoxy resin. A core conductor layer 4made of copper foil or a copper plating layer is adhered to the upperand lower surfaces of the core substrate 1. A number of through-holes 5are formed so as to extend from the upper surface to the lower surfaceof the core substrate 1 (insulating board), and the copper plating layerserving as a part of the core conductor layer 4 is adhered to an innerperipheral surface of the through-hole 5. The through-hole 5 has adiameter of about 100 μm to 300 μm. The through-hole 5 is filled with aresin.

The buildup insulating layer 2 has a thickness of about 20 μm to 50 μm.The buildup insulating layer 2 is made of an electric insulatingmaterial obtained by dispersing an inorganic insulating filler such as asilicon oxide into a thermosetting resin such as an epoxy resin. Eachbuildup insulating layer 2 is provided with a plurality of via-holes 6each having a diameter of about 35 μm to 100 μm.

The buildup wiring layer 3 is adhered to a surface of the buildupinsulating layer 2 and an inner surface of the via-hole 6. The buildupwiring layer 3 is electrically connected to the through-hole 5.

Circular semiconductor element connection pads 7 are formed as a part ofthe outermost buildup wiring layer 3 located on a side of the uppersurface of the wiring board 10. These semiconductor element connectionpads 7 are arranged in a lattice-like form. An outer peripheral portionof the semiconductor element connection pad 7 is covered with a solderresist layer 9. A center of an upper surface of the semiconductorelement connection pad 7 is not covered with the solder resist layer 9so as to be exposed. The exposed portion of the semiconductor elementconnection pad 7 is electrically connected to an electrode T of asemiconductor element S through a soldering bump B.

On the other hand, circular external connection pads 8 are formed as apart of the outermost buildup wiring layer 3 located on a side of thelower surface of the wiring board 10. These external connection pads 8are arranged in a lattice-like form. An outer peripheral portion of theexternal connection pad 8 is covered with the solder resist layer 9. Acenter of a lower surface of the external connection pad 8 is notcovered with the solder resist layer 9 so as to be exposed. The exposedpart of the external connection pad 8 is electrically connected to awiring conductor of an external electric circuit board (not shown)through a soldering ball. The solder resist layer 9 protects theoutermost buildup wiring layer 3, and defines the exposed portions ofeach of the semiconductor element connection pads 7 and the externalconnection pads 8.

In order to ensure sufficient power supply from the wiring board 10, thesemiconductor element S has a terminal arrangement in which a number ofgrounding and power supply electrodes T are provided in a center of itslower surface, and a number of signal electrodes T are provided in anouter peripheral potion of its lower surface.

According to the wiring board 10 for mounting the semiconductor elementS, as shown in FIG. 2, a number of grounding through-holes 5G and anumber of power supply through-holes 5P (first through-hole group) areprovided in a first region X opposed to a semiconductor elementconnection pad formation region A, at a high arrangement density (firstarrangement density).

A number of signal through-holes 5S (second through-hole group) areprovided in a second region Y, which is located in an outer periphery ofthe core substrate 1 and away from the first region X, at an arrangementdensity (second arrangement density) lower than the arrangement density(first arrangement density) of the through-holes 5G and 5P in the firstregion X.

Since the grounding through-holes 5G and the power supply through-holes5P are provided in the first region X at the high arrangement density,it is possible to connect the grounding semiconductor element connectionpad 7 to the grounding through-hole 5G, and the power supplysemiconductor element connection pad 7 to the power supply through-hole5P within a short distance.

The grounding external connection pad 8 and the power supply externalconnection pad 8 are arranged in a center of a lower surface of thewiring board 10. Thus, it is possible to connect the groundingthrough-hole 5G to the grounding external connection pad 8, and thepower supply through-hole 5P to the power supply external connection pad8 within a short distance.

As a result, an inductance is low in each of current paths forconnecting the grounding semiconductor element connection pad 7 to thegrounding external connection pad 8, and the power supply semiconductorelement connection pad 7 to the power supply external connection pad 8,so that the power can be sufficiently supplied to the semiconductorelement S.

In the core substrate 1 of the wiring board 10, dummy through-holes 5D(third through-hole group) are provided in a third region Z locatedbetween the first region X and the second region Y. It is preferablethat an arrangement density (third arrangement density) of the dummythrough-holes 5D is higher than the arrangement density of thethrough-holes 5S in the second region Y, and is equal to or smaller thanthe arrangement density of the through-holes 5G and 5P in the firstregion X. The dummy through-hole 5D is not electrically connected to thevia-hole 6.

An arrangement pitch of the through-holes 5 in the third region Z ispreferably 1.6 times or less with respect to an arrangement pitch of thethrough-holes 5G and 5P in the region X. The arrangement pitch is apitch of the through-holes 5 in a vertical direction and a horizontaldirection in a plane shown in FIG. 2.

In the core substrate 1, the dummy through-holes 5D are provided in thethird region Z located between the first region X and the second regionY, at the arrangement density (third arrangement density) higher thanthe arrangement density (second arrangement density) of thethrough-holes 5S arranged in the second region Y. Thus, behaviors ofthermal expansion and thermal shrinkage, and a position of a stiffnesschange due to a difference in arrangement density of the through-holes 5are provided away from the region X corresponding to the semiconductorelement connection pad formation region A.

As described above, the behaviors of the thermal expansion and thermalshrinkage and the position of the stiffness change due to the differencein arrangement density of the through-holes 5 are provided away from thefirst region X corresponding to the semiconductor element connection padformation region A. Thus, as shown in FIG. 3, when the electrode T ofthe semiconductor element S is connected to the semiconductor elementconnection pad 7 through the soldering bump B, an impact on thesemiconductor element connection pad formation region A becomes small,and warpage can be made small in the semiconductor element connectionpad formation region A. As a result, it is possible to prevent thedistance from being reduced between the electrode T of the semiconductorelement S and the semiconductor element connection pad 7 in the outerperipheral portion, so that the soldering bump B is not severelycrushed. Therefore, according to the wiring board 10, an electricalshort circuit is not caused between the adjacent soldering bumps B, andthe mounted semiconductor element S can be normally operated.

The dummy through-hole 5D may be electrically independent, or may beelectrically connected to a grounding potential or a power supplypotential. The through-hole 5 may be filled with copper plating insteadof being filled with the resin.

What is claimed is:
 1. A wiring board comprising: a core substratehaving a number of through-holes; and buildup insulating layers andbuildup wiring layers alternately laminated on upper and lower surfacesof the core substrate, the wiring board having a semiconductor elementconnection pad formation region where a number of semiconductor elementconnection pads made of the buildup wiring layer are arranged in alattice-like form in a center of an upper surface, wherein a firstthrough-hole group is arranged in a first region in the core substrateat a first arrangement density, the first region being opposed to thesemiconductor element connection pad formation region, a secondthrough-hole group is arranged in a second region at a secondarrangement density lower than the first arrangement density, the secondregion being located in an outer peripheral portion of the coresubstrate and away from the first region, and a third through-hole groupis arranged in a third region at a third arrangement density higher thanthe second arrangement density, the third region being located betweenthe first region and the second region.
 2. The wiring board according toclaim 1, wherein external connection pads made of the buildup wiringlayer are arranged in a center of a lower surface.
 3. The wiring boardaccording to claim 1, wherein the third arrangement density is equal toor smaller than the first arrangement density.
 4. The wiring boardaccording to claim 1, wherein the first through-hole group includes agrounding through-hole and a power supply through-hole.
 5. The wiringboard according to claim 1, wherein the second through-hole groupincludes a signal through-hole.
 6. The wiring board according to claim1, wherein the third through-hole group includes a dummy through-hole.